WEBVTT 00:00:00.000 --> 00:00:05.340 align:middle line:90% 00:00:05.340 --> 00:00:05.970 align:middle line:90% Hello. 00:00:05.970 --> 00:00:11.040 align:middle line:84% Welcome to the 2022 Power Supply Design Seminar. 00:00:11.040 --> 00:00:14.550 align:middle line:84% The presentation topic is isolated gate-driver bias 00:00:14.550 --> 00:00:17.220 align:middle line:90% supply design considerations. 00:00:17.220 --> 00:00:18.960 align:middle line:90% My name is Brent McDonald. 00:00:18.960 --> 00:00:22.540 align:middle line:84% I'm a system engineer inside our Power Supply Design Services 00:00:22.540 --> 00:00:23.040 align:middle line:90% Group. 00:00:23.040 --> 00:00:26.270 align:middle line:90% 00:00:26.270 --> 00:00:29.040 align:middle line:84% Here is the agenda for the presentation. 00:00:29.040 --> 00:00:31.190 align:middle line:84% First I'll give a brief introduction 00:00:31.190 --> 00:00:34.610 align:middle line:84% of the inverter and isolated gate-driver bias supply 00:00:34.610 --> 00:00:36.110 align:middle line:90% architectures. 00:00:36.110 --> 00:00:39.050 align:middle line:84% Followed by that, we'll discuss several different ways 00:00:39.050 --> 00:00:43.220 align:middle line:84% of creating isolated bias supplies, including the control 00:00:43.220 --> 00:00:47.090 align:middle line:84% methods, different topologies, as well as the transformer 00:00:47.090 --> 00:00:49.070 align:middle line:90% construction methods. 00:00:49.070 --> 00:00:52.490 align:middle line:84% Based on the comparison of different isolated bias supply 00:00:52.490 --> 00:00:57.320 align:middle line:84% solutions, the LLC-based open-loop isolated bias supply 00:00:57.320 --> 00:00:59.450 align:middle line:90% is going to be introduced. 00:00:59.450 --> 00:01:02.750 align:middle line:84% The discussion covers the circuit operation principles 00:01:02.750 --> 00:01:07.640 align:middle line:84% and the circuit variations, its voltage regulation is derived, 00:01:07.640 --> 00:01:11.780 align:middle line:84% and the methods of creating multiple outputs are discussed. 00:01:11.780 --> 00:01:15.170 align:middle line:84% The design procedure is also introduced. 00:01:15.170 --> 00:01:18.500 align:middle line:84% Finally, we'll give some performance demonstration 00:01:18.500 --> 00:01:22.385 align:middle line:84% of the LLC-based open-loop isolated bias supply. 00:01:22.385 --> 00:01:26.220 align:middle line:90% 00:01:26.220 --> 00:01:29.100 align:middle line:84% The isolated gate driver is a key component 00:01:29.100 --> 00:01:32.850 align:middle line:84% in many power electronic systems, including the traction 00:01:32.850 --> 00:01:35.430 align:middle line:84% inverter in the electric vehicle-- 00:01:35.430 --> 00:01:39.090 align:middle line:84% the motor drive, the UPS system, as well as 00:01:39.090 --> 00:01:44.620 align:middle line:84% in the onboard charger of an electric car. 00:01:44.620 --> 00:01:47.740 align:middle line:84% As shown in this picture, the isolated gate drivers 00:01:47.740 --> 00:01:51.070 align:middle line:84% are normally located very close to the inverter power 00:01:51.070 --> 00:01:55.405 align:middle line:84% stage and allow the MCU to control the power stage. 00:01:55.405 --> 00:02:00.090 align:middle line:90% 00:02:00.090 --> 00:02:03.870 align:middle line:84% Here shows an example of the automotive traction inverter, 00:02:03.870 --> 00:02:06.690 align:middle line:84% how the circuits are biased and controlled. 00:02:06.690 --> 00:02:09.570 align:middle line:84% There are two power sources in this system-- 00:02:09.570 --> 00:02:13.530 align:middle line:84% the low-voltage battery and the high-voltage battery. 00:02:13.530 --> 00:02:17.730 align:middle line:84% The inverter is directly powered by the high-voltage battery, 00:02:17.730 --> 00:02:19.890 align:middle line:84% while the control circuit is biased 00:02:19.890 --> 00:02:24.260 align:middle line:84% by both the high-voltage and low-voltage batteries. 00:02:24.260 --> 00:02:28.820 align:middle line:84% The high-voltage is processed by an isolated DC-to-DC converter, 00:02:28.820 --> 00:02:33.040 align:middle line:84% and then [? org ?] together with the low-voltage battery 00:02:33.040 --> 00:02:37.060 align:middle line:84% to create a reliable bus voltage and then processed 00:02:37.060 --> 00:02:40.300 align:middle line:84% to the other regulated bus voltages. 00:02:40.300 --> 00:02:43.270 align:middle line:84% The control signals coming from the MCU 00:02:43.270 --> 00:02:45.970 align:middle line:84% are passed through the isolated gate driver 00:02:45.970 --> 00:02:48.700 align:middle line:84% to control the inverter power stages. 00:02:48.700 --> 00:02:53.170 align:middle line:84% You can see the three low-side drivers share the same ground, 00:02:53.170 --> 00:02:57.160 align:middle line:84% but each of the high-side drivers has its own ground. 00:02:57.160 --> 00:03:00.070 align:middle line:84% Given that there are so many grounds in the system, 00:03:00.070 --> 00:03:03.970 align:middle line:84% there is a need to create many isolated bias supplies 00:03:03.970 --> 00:03:06.760 align:middle line:90% for the isolated gate drivers. 00:03:06.760 --> 00:03:08.380 align:middle line:90% How do we do that? 00:03:08.380 --> 00:03:12.550 align:middle line:90% 00:03:12.550 --> 00:03:14.920 align:middle line:84% To design the isolated bias supplies, 00:03:14.920 --> 00:03:18.850 align:middle line:84% first we need to understand the requirements, including 00:03:18.850 --> 00:03:21.280 align:middle line:84% output voltages, voltage regulation 00:03:21.280 --> 00:03:23.890 align:middle line:90% requirements, and power levels. 00:03:23.890 --> 00:03:26.050 align:middle line:84% In many designs, the gate drivers 00:03:26.050 --> 00:03:28.810 align:middle line:84% often have positive and negative supplies, 00:03:28.810 --> 00:03:30.740 align:middle line:90% as shown in this picture. 00:03:30.740 --> 00:03:32.980 align:middle line:84% The gate-driver loss can be calculated 00:03:32.980 --> 00:03:36.760 align:middle line:84% using the driving voltage, the gate charge, and the switching 00:03:36.760 --> 00:03:37.780 align:middle line:90% frequency. 00:03:37.780 --> 00:03:39.940 align:middle line:84% The driving voltage requirements are 00:03:39.940 --> 00:03:42.640 align:middle line:84% different for different power devices. 00:03:42.640 --> 00:03:45.730 align:middle line:84% Silicon carbide and silicon MOSFETs 00:03:45.730 --> 00:03:47.840 align:middle line:90% are shown as an example. 00:03:47.840 --> 00:03:50.710 align:middle line:84% The plot shows the driver voltage impact 00:03:50.710 --> 00:03:54.340 align:middle line:90% on the RDS(on) of these devices. 00:03:54.340 --> 00:03:57.220 align:middle line:84% The curves show the normalized RDS(on) 00:03:57.220 --> 00:04:01.630 align:middle line:84% for four different MOSFETs, with their RDS(on) measured 00:04:01.630 --> 00:04:05.420 align:middle line:90% at 20 volts gate voltage. 00:04:05.420 --> 00:04:10.010 align:middle line:84% With the increase of their gate voltage, the RDS(on) reduces. 00:04:10.010 --> 00:04:12.890 align:middle line:84% It can be noticed that for the silicon FET, when 00:04:12.890 --> 00:04:17.970 align:middle line:84% the gate voltage is above 10 volts, the RDS(on) saturates. 00:04:17.970 --> 00:04:20.250 align:middle line:84% Further increases in the gate voltage 00:04:20.250 --> 00:04:24.600 align:middle line:84% will not reduce the conduction loss and the gate-driver loss 00:04:24.600 --> 00:04:25.750 align:middle line:90% increases. 00:04:25.750 --> 00:04:29.190 align:middle line:84% This means the driving voltage for the silicon FET 00:04:29.190 --> 00:04:32.520 align:middle line:84% should only be slightly higher than 10 volts 00:04:32.520 --> 00:04:36.900 align:middle line:84% to get the lowest conduction loss and driver loss. 00:04:36.900 --> 00:04:39.540 align:middle line:84% Normally, we see people drive these devices 00:04:39.540 --> 00:04:43.920 align:middle line:84% with 12 or 15 volts of gate voltage. 00:04:43.920 --> 00:04:46.770 align:middle line:84% And there is not much need for the gate voltage 00:04:46.770 --> 00:04:49.440 align:middle line:84% to be very accurately controlled. 00:04:49.440 --> 00:04:51.990 align:middle line:84% For the silicon carbide MOSFETs, the behavior 00:04:51.990 --> 00:04:53.190 align:middle line:90% is quite different. 00:04:53.190 --> 00:04:57.720 align:middle line:84% Their RDS(on) keeps reducing with the increasing of the gate 00:04:57.720 --> 00:04:58.810 align:middle line:90% voltage. 00:04:58.810 --> 00:05:01.270 align:middle line:90% There is no sign of saturation. 00:05:01.270 --> 00:05:05.040 align:middle line:84% This means that the dry voltage needs to be as high as possible 00:05:05.040 --> 00:05:07.380 align:middle line:90% to reduce the conduction loss. 00:05:07.380 --> 00:05:10.440 align:middle line:84% This driver voltage could be very close to the gate 00:05:10.440 --> 00:05:12.040 align:middle line:90% breakdown voltage. 00:05:12.040 --> 00:05:15.270 align:middle line:84% Therefore, you can see the gate-driver voltage 00:05:15.270 --> 00:05:20.790 align:middle line:84% is 18 or 20 volts with a tight regulation requirement, 00:05:20.790 --> 00:05:24.880 align:middle line:90% like somewhere between 1% to 5%. 00:05:24.880 --> 00:05:29.440 align:middle line:84% The IGBT behavior is similar to a silicon FET. 00:05:29.440 --> 00:05:34.060 align:middle line:84% It is normally driven by a 15 or 18 volt gate voltage, 00:05:34.060 --> 00:05:38.000 align:middle line:84% with less concerns on the gate voltage accuracy. 00:05:38.000 --> 00:05:40.360 align:middle line:84% The negative voltage is often needed 00:05:40.360 --> 00:05:45.460 align:middle line:84% to speed up the turn-off process and reduce the switching loss. 00:05:45.460 --> 00:05:48.970 align:middle line:84% Or, it is also added to prevent shoot-through. 00:05:48.970 --> 00:05:52.900 align:middle line:84% This table summarizes the typical gate-driver voltage 00:05:52.900 --> 00:05:55.195 align:middle line:84% requirements for different devices. 00:05:55.195 --> 00:05:58.690 align:middle line:90% 00:05:58.690 --> 00:06:02.680 align:middle line:84% After the power requirement, the bias supply architecture 00:06:02.680 --> 00:06:04.360 align:middle line:90% needs to be determined. 00:06:04.360 --> 00:06:07.000 align:middle line:84% There are six isolated gate drivers 00:06:07.000 --> 00:06:09.430 align:middle line:90% in a three-phase inverter. 00:06:09.430 --> 00:06:13.960 align:middle line:84% The centralized architecture creates all the isolated bias 00:06:13.960 --> 00:06:17.270 align:middle line:84% supply rails using a single converter. 00:06:17.270 --> 00:06:20.350 align:middle line:84% This gives a lowest cost solution 00:06:20.350 --> 00:06:23.330 align:middle line:84% because only one power supply is needed. 00:06:23.330 --> 00:06:26.620 align:middle line:84% However, the transformer needs to handle the total power 00:06:26.620 --> 00:06:28.720 align:middle line:90% of all the gate drivers. 00:06:28.720 --> 00:06:31.810 align:middle line:84% The transformer can be heavy and bulky. 00:06:31.810 --> 00:06:34.990 align:middle line:84% It becomes a challenge when the system needs 00:06:34.990 --> 00:06:37.510 align:middle line:90% to pass the vibration test. 00:06:37.510 --> 00:06:40.600 align:middle line:84% Instead of using a single converter, 00:06:40.600 --> 00:06:45.370 align:middle line:84% several converters can be used, all three low-side devices 00:06:45.370 --> 00:06:47.650 align:middle line:90% sharing the same ground. 00:06:47.650 --> 00:06:51.250 align:middle line:84% They can be powered from a single power supply. 00:06:51.250 --> 00:06:55.510 align:middle line:84% Each of the three high-side drivers has its own ground. 00:06:55.510 --> 00:06:59.500 align:middle line:84% Each one of them needs its own isolated bias supply. 00:06:59.500 --> 00:07:03.730 align:middle line:84% We'll call this a semi-distributed architecture. 00:07:03.730 --> 00:07:08.020 align:middle line:84% You can go one step further and make a fully distributed 00:07:08.020 --> 00:07:09.310 align:middle line:90% architecture. 00:07:09.310 --> 00:07:15.790 align:middle line:84% Each isolated gate driver is biased by its own bias supply. 00:07:15.790 --> 00:07:18.830 align:middle line:84% Comparing these three architectures, 00:07:18.830 --> 00:07:23.080 align:middle line:84% we can see that the centralized system has the lowest cost. 00:07:23.080 --> 00:07:25.780 align:middle line:84% But the bulky and heavy transformer 00:07:25.780 --> 00:07:29.290 align:middle line:84% makes it more difficult to pass the vibration test. 00:07:29.290 --> 00:07:32.530 align:middle line:84% Another concern is the fault management. 00:07:32.530 --> 00:07:35.950 align:middle line:84% Because everything comes from a single power supply, 00:07:35.950 --> 00:07:39.760 align:middle line:90% once it fails, everything fails. 00:07:39.760 --> 00:07:43.060 align:middle line:84% The distributed system goes to another extreme. 00:07:43.060 --> 00:07:47.690 align:middle line:84% It has sixth power supplies and it carries more cost. 00:07:47.690 --> 00:07:51.670 align:middle line:84% However, the transformer is spread out to six transformers. 00:07:51.670 --> 00:07:55.210 align:middle line:84% And it is much easier to pass the vibration test. 00:07:55.210 --> 00:07:58.900 align:middle line:84% Besides, it has six individual power supplies. 00:07:58.900 --> 00:08:03.220 align:middle line:84% One power supply failure won't cause the entire system 00:08:03.220 --> 00:08:04.150 align:middle line:90% failure. 00:08:04.150 --> 00:08:07.540 align:middle line:84% The fault management becomes much easier. 00:08:07.540 --> 00:08:10.240 align:middle line:84% The semi-distributed system gives 00:08:10.240 --> 00:08:13.570 align:middle line:84% a trade-off between the cost and reliability. 00:08:13.570 --> 00:08:16.930 align:middle line:84% It becomes a popular solution for the automotive industry. 00:08:16.930 --> 00:08:20.690 align:middle line:90% 00:08:20.690 --> 00:08:24.080 align:middle line:84% After selecting the appropriate system architecture, 00:08:24.080 --> 00:08:26.450 align:middle line:84% the next question needs to be answered 00:08:26.450 --> 00:08:29.930 align:middle line:84% is, how to control the output voltage. 00:08:29.930 --> 00:08:33.860 align:middle line:84% For an isolated power supply, the most popular control method 00:08:33.860 --> 00:08:36.830 align:middle line:84% is to use the closed loop control 00:08:36.830 --> 00:08:38.870 align:middle line:90% with secondary-side feedback. 00:08:38.870 --> 00:08:42.710 align:middle line:84% The output voltage is directly sensed on the secondary side, 00:08:42.710 --> 00:08:46.010 align:middle line:84% passed through the control loop, then the control signal 00:08:46.010 --> 00:08:49.220 align:middle line:84% is transferred through the optocoupler 00:08:49.220 --> 00:08:50.810 align:middle line:90% to the primary side. 00:08:50.810 --> 00:08:54.620 align:middle line:84% And the primary side controller controls the duty cycle 00:08:54.620 --> 00:08:58.260 align:middle line:84% or switching frequency to regulate the output voltage. 00:08:58.260 --> 00:09:01.820 align:middle line:84% This control method directly senses the output voltage 00:09:01.820 --> 00:09:04.250 align:middle line:90% with closed loop control. 00:09:04.250 --> 00:09:07.430 align:middle line:84% It gives a well-regulated output. 00:09:07.430 --> 00:09:10.220 align:middle line:90% Its input can have a wide range. 00:09:10.220 --> 00:09:12.290 align:middle line:90% No pre-regulator is needed. 00:09:12.290 --> 00:09:16.460 align:middle line:84% However, it requires a lot of components for the sensing, 00:09:16.460 --> 00:09:18.920 align:middle line:90% control loop, and isolation. 00:09:18.920 --> 00:09:21.590 align:middle line:84% Besides, the optocoupler generally 00:09:21.590 --> 00:09:23.960 align:middle line:90% has a lower reliability. 00:09:23.960 --> 00:09:27.380 align:middle line:84% People try to avoid using it in the applications 00:09:27.380 --> 00:09:30.090 align:middle line:90% where reliability is critical-- 00:09:30.090 --> 00:09:33.590 align:middle line:84% for example, in an automotive system. 00:09:33.590 --> 00:09:37.220 align:middle line:84% To improve the reliability, the optocoupler 00:09:37.220 --> 00:09:41.480 align:middle line:84% can be removed by using the primary-side feedback method. 00:09:41.480 --> 00:09:45.320 align:middle line:84% Instead of directly sensing the output voltage, 00:09:45.320 --> 00:09:48.440 align:middle line:84% the output voltage is sensed on the primary side 00:09:48.440 --> 00:09:51.960 align:middle line:90% through transformer coupling. 00:09:51.960 --> 00:09:55.350 align:middle line:84% The output voltage can then be regulated on the primary side 00:09:55.350 --> 00:09:57.450 align:middle line:90% without using an optocoupler. 00:09:57.450 --> 00:10:00.300 align:middle line:84% Since it can still sense the output voltage, 00:10:00.300 --> 00:10:03.240 align:middle line:84% it can take a wide input voltage range 00:10:03.240 --> 00:10:06.060 align:middle line:84% without requiring a pre-regulator. 00:10:06.060 --> 00:10:09.330 align:middle line:84% Because the output voltage is sensed indirectly, 00:10:09.330 --> 00:10:11.430 align:middle line:84% the voltage regulation performance 00:10:11.430 --> 00:10:15.330 align:middle line:84% is not as good as the secondary-side control. 00:10:15.330 --> 00:10:18.120 align:middle line:84% But it could be good enough for most 00:10:18.120 --> 00:10:20.400 align:middle line:90% of the gate-driver application. 00:10:20.400 --> 00:10:23.820 align:middle line:84% To improve the output voltage sensing accuracy, 00:10:23.820 --> 00:10:28.140 align:middle line:84% the converter has to operate in discontinuous conduction mode 00:10:28.140 --> 00:10:32.610 align:middle line:84% and the output voltage has to be sensed at a specific point. 00:10:32.610 --> 00:10:35.250 align:middle line:84% This makes the voltage sampling method 00:10:35.250 --> 00:10:38.310 align:middle line:90% more susceptible to noise. 00:10:38.310 --> 00:10:40.590 align:middle line:84% Another way of controlling the output 00:10:40.590 --> 00:10:45.930 align:middle line:84% is to use an open-loop control for certain type of power 00:10:45.930 --> 00:10:49.860 align:middle line:84% converters when it's operation condition is fixed. 00:10:49.860 --> 00:10:54.750 align:middle line:84% For example, 50% duty cycle or fixed switching frequency, 00:10:54.750 --> 00:10:57.510 align:middle line:84% there is a fixed relationship between the input 00:10:57.510 --> 00:10:59.940 align:middle line:90% voltage and the output voltage. 00:10:59.940 --> 00:11:05.030 align:middle line:84% And the power supply can be controlled with open loop. 00:11:05.030 --> 00:11:08.390 align:middle line:84% With fixed input voltage, a fixed output voltage 00:11:08.390 --> 00:11:09.710 align:middle line:90% can be created. 00:11:09.710 --> 00:11:14.870 align:middle line:84% Apparently, this power supply needs a fixed input voltage. 00:11:14.870 --> 00:11:19.730 align:middle line:84% With a variable input voltage, a pre-regulator is needed. 00:11:19.730 --> 00:11:23.150 align:middle line:84% Also, the output voltage is unregulated. 00:11:23.150 --> 00:11:25.520 align:middle line:84% It changes slightly with the load condition 00:11:25.520 --> 00:11:28.730 align:middle line:84% depending on how much circuit loss it has. 00:11:28.730 --> 00:11:31.070 align:middle line:84% However, because the control method 00:11:31.070 --> 00:11:33.680 align:middle line:84% doesn't need to sense the output voltage 00:11:33.680 --> 00:11:38.360 align:middle line:84% or have the control loop, it is more immune to noise 00:11:38.360 --> 00:11:39.920 align:middle line:90% and always stable. 00:11:39.920 --> 00:11:42.980 align:middle line:90% It also uses less components. 00:11:42.980 --> 00:11:47.870 align:middle line:84% The open-loop control provides a low-cost and reliable solution 00:11:47.870 --> 00:11:51.150 align:middle line:84% for the isolated gate-driver bias supply. 00:11:51.150 --> 00:11:54.890 align:middle line:84% And it is more attractive in the noisy environment, 00:11:54.890 --> 00:11:59.240 align:middle line:84% such as the industrial or automotive application. 00:11:59.240 --> 00:12:02.950 align:middle line:90% 00:12:02.950 --> 00:12:06.510 align:middle line:84% The next step is to choose the right topology. 00:12:06.510 --> 00:12:09.090 align:middle line:84% The isolated bias supply is basically 00:12:09.090 --> 00:12:11.820 align:middle line:90% an isolated DC-to-DC converter. 00:12:11.820 --> 00:12:14.220 align:middle line:90% Many topologies can be used. 00:12:14.220 --> 00:12:18.180 align:middle line:84% Here, we will give several examples. 00:12:18.180 --> 00:12:22.410 align:middle line:84% The flyback converter is the simplest isolated DC-to-DC 00:12:22.410 --> 00:12:23.220 align:middle line:90% converter. 00:12:23.220 --> 00:12:27.540 align:middle line:84% It uses one switch, one diode, and one transformer 00:12:27.540 --> 00:12:30.450 align:middle line:84% to create the isolated bias supply. 00:12:30.450 --> 00:12:32.910 align:middle line:84% It can easily create multiple outputs 00:12:32.910 --> 00:12:36.030 align:middle line:84% by adding more windings to the transformer. 00:12:36.030 --> 00:12:38.670 align:middle line:84% Each output voltage is proportional to the turns 00:12:38.670 --> 00:12:39.630 align:middle line:90% ratio. 00:12:39.630 --> 00:12:44.260 align:middle line:84% And it is very suitable for the centralized architecture. 00:12:44.260 --> 00:12:48.460 align:middle line:84% Traditionally, multiple output flyback converters 00:12:48.460 --> 00:12:51.790 align:middle line:84% have a concern about cross regulation. 00:12:51.790 --> 00:12:54.680 align:middle line:84% When the load conditions are different, 00:12:54.680 --> 00:12:57.830 align:middle line:84% the output voltage regulation could be bad. 00:12:57.830 --> 00:13:00.070 align:middle line:84% However, this is less of an issue 00:13:00.070 --> 00:13:03.490 align:middle line:84% in the isolated gate-driver application 00:13:03.490 --> 00:13:07.570 align:middle line:84% because the gate-driver loads are normally well-balanced. 00:13:07.570 --> 00:13:09.970 align:middle line:84% The flyback converter can be controlled 00:13:09.970 --> 00:13:14.110 align:middle line:84% with secondary-side or primary-side feedback. 00:13:14.110 --> 00:13:18.010 align:middle line:84% Normally, we are not using flyback converters 00:13:18.010 --> 00:13:21.370 align:middle line:90% with open open-loop control. 00:13:21.370 --> 00:13:24.400 align:middle line:84% The push-pull converter is another popular choice 00:13:24.400 --> 00:13:26.410 align:middle line:90% because of its simplicity. 00:13:26.410 --> 00:13:28.960 align:middle line:84% It uses a bit more components compared 00:13:28.960 --> 00:13:30.680 align:middle line:90% with the flyback converter. 00:13:30.680 --> 00:13:33.670 align:middle line:84% However, the transformer utilization is better. 00:13:33.670 --> 00:13:36.640 align:middle line:84% It can be used with open-loop control. 00:13:36.640 --> 00:13:41.680 align:middle line:84% When both switches operate with 50% complementary duty cycle, 00:13:41.680 --> 00:13:44.710 align:middle line:84% the output voltage is connected with the input voltage 00:13:44.710 --> 00:13:47.470 align:middle line:84% directly through the transformer. 00:13:47.470 --> 00:13:50.680 align:middle line:84% Therefore, the relationship between the input and output 00:13:50.680 --> 00:13:54.520 align:middle line:84% voltage is simply the transformer turns ratio. 00:13:54.520 --> 00:13:57.610 align:middle line:84% It can also be used with closed-loop control. 00:13:57.610 --> 00:14:01.720 align:middle line:84% In this case, the duty cycle will be less than 50% 00:14:01.720 --> 00:14:06.430 align:middle line:84% to regulate the output voltage and an output filter inductor 00:14:06.430 --> 00:14:08.680 align:middle line:90% is required. 00:14:08.680 --> 00:14:12.430 align:middle line:84% Another option is to use a half-bridge or full-bridge 00:14:12.430 --> 00:14:13.210 align:middle line:90% converter. 00:14:13.210 --> 00:14:15.550 align:middle line:84% Here I show a half-bridge converter. 00:14:15.550 --> 00:14:18.400 align:middle line:84% It is very similar to the push-pull converter 00:14:18.400 --> 00:14:21.440 align:middle line:90% with 50% duty cycle operation. 00:14:21.440 --> 00:14:24.520 align:middle line:84% The output voltage is connected with the input voltage 00:14:24.520 --> 00:14:26.230 align:middle line:90% through the transformer. 00:14:26.230 --> 00:14:30.010 align:middle line:84% There is a fixed relationship between the input and output 00:14:30.010 --> 00:14:31.100 align:middle line:90% voltage. 00:14:31.100 --> 00:14:35.680 align:middle line:84% This circuit can be implemented with a simple gate-driver IC 00:14:35.680 --> 00:14:40.150 align:middle line:84% with a timer to create 50% duty cycle. 00:14:40.150 --> 00:14:45.130 align:middle line:84% Both the push-pull and half or full-bridge converters 00:14:45.130 --> 00:14:49.810 align:middle line:84% are good for the distributed and semi-distributed architectures. 00:14:49.810 --> 00:14:52.640 align:middle line:90% 00:14:52.640 --> 00:14:55.730 align:middle line:84% Regardless of which circuit topology we choose, 00:14:55.730 --> 00:15:00.080 align:middle line:84% the transformer is a key element in the isolated bias supply. 00:15:00.080 --> 00:15:02.840 align:middle line:84% The transformer parameters can largely 00:15:02.840 --> 00:15:06.830 align:middle line:84% impact the overall system EMI performance. 00:15:06.830 --> 00:15:10.470 align:middle line:84% Here, we use a three-phase inverter as an example. 00:15:10.470 --> 00:15:13.640 align:middle line:84% Looking at the high-side gate driver of the first leg, 00:15:13.640 --> 00:15:16.460 align:middle line:84% the isolated bias supply gets its power 00:15:16.460 --> 00:15:20.870 align:middle line:84% from the low-voltage supply and transfers it to the high side. 00:15:20.870 --> 00:15:23.720 align:middle line:84% Its output voltage ground is connected 00:15:23.720 --> 00:15:25.640 align:middle line:90% with the inverter switch node. 00:15:25.640 --> 00:15:29.780 align:middle line:84% Looking into the details of this isolated bias supply, when 00:15:29.780 --> 00:15:35.210 align:middle line:84% the output ground fluctuates with the inverter power stage 00:15:35.210 --> 00:15:38.360 align:middle line:84% switch node, the high dv/dt can be 00:15:38.360 --> 00:15:40.580 align:middle line:84% coupled through the parasitic capacitor 00:15:40.580 --> 00:15:44.900 align:middle line:84% between the transformer primary and secondary sides. 00:15:44.900 --> 00:15:49.070 align:middle line:84% We often call this cap an interwinding capacitor. 00:15:49.070 --> 00:15:53.690 align:middle line:84% This current can cause high EMI noise, extra power loss. 00:15:53.690 --> 00:15:56.090 align:middle line:84% And the noise current can potentially 00:15:56.090 --> 00:16:03.020 align:middle line:84% cause a CMTI issue, also known as Common-Mode Transient 00:16:03.020 --> 00:16:05.490 align:middle line:90% Immunity issue. 00:16:05.490 --> 00:16:08.970 align:middle line:84% The controller could also malfunction or trigger 00:16:08.970 --> 00:16:12.600 align:middle line:84% protection mechanisms because of this noise current. 00:16:12.600 --> 00:16:16.410 align:middle line:84% The noise becomes more severe when the wide bandgap 00:16:16.410 --> 00:16:20.640 align:middle line:84% devices are used, such as silicon carbide or GaN. 00:16:20.640 --> 00:16:23.250 align:middle line:84% Because the dv/dt is much higher, 00:16:23.250 --> 00:16:27.240 align:middle line:84% we often hear of 50 volts per nanosecond 00:16:27.240 --> 00:16:31.320 align:middle line:84% or even 100 volts per nanosecond of voltage slew rate 00:16:31.320 --> 00:16:33.730 align:middle line:90% with these devices. 00:16:33.730 --> 00:16:35.650 align:middle line:90% Here is some simple math. 00:16:35.650 --> 00:16:39.250 align:middle line:84% With 100 volts per nanoseconds of dv/dt, 00:16:39.250 --> 00:16:43.480 align:middle line:84% even a 1 picofarad parasitic cap can cause 00:16:43.480 --> 00:16:46.210 align:middle line:90% 0.1 amps of noise current. 00:16:46.210 --> 00:16:49.810 align:middle line:84% And we normally see about 20 to 30 picofarads 00:16:49.810 --> 00:16:54.040 align:middle line:84% of interwinding capacitance for a flyback transformer. 00:16:54.040 --> 00:16:57.610 align:middle line:84% It is clear that a good, isolated bias 00:16:57.610 --> 00:17:00.400 align:middle line:84% supply for the isolated gate driver 00:17:00.400 --> 00:17:04.750 align:middle line:84% should have a very low interwinding capacitance. 00:17:04.750 --> 00:17:08.310 align:middle line:90% 00:17:08.310 --> 00:17:11.220 align:middle line:84% So how do we make the interwinding capacitance 00:17:11.220 --> 00:17:12.630 align:middle line:90% smaller? 00:17:12.630 --> 00:17:16.920 align:middle line:84% Here we see a typical way of making a transformer. 00:17:16.920 --> 00:17:21.750 align:middle line:84% Outside is the core and inside are the bobbin and windings. 00:17:21.750 --> 00:17:26.079 align:middle line:84% The windings are put on the bobbin by layers-- 00:17:26.079 --> 00:17:29.350 align:middle line:84% first, the primary layer, then the insulator, 00:17:29.350 --> 00:17:32.310 align:middle line:90% then the secondary layer. 00:17:32.310 --> 00:17:36.120 align:middle line:84% The capacitance can be estimated by this equation. 00:17:36.120 --> 00:17:39.540 align:middle line:84% Reducing the surface area or increasing the distance 00:17:39.540 --> 00:17:41.700 align:middle line:90% can reduce the capacitance. 00:17:41.700 --> 00:17:46.230 align:middle line:84% One easy way is to increase the insulator thickness-- 00:17:46.230 --> 00:17:48.930 align:middle line:84% basically, increase the distance. 00:17:48.930 --> 00:17:53.350 align:middle line:84% This is less effective because of the large surface area. 00:17:53.350 --> 00:17:55.950 align:middle line:84% Another way of reducing the capacitance 00:17:55.950 --> 00:18:00.370 align:middle line:84% is to use a split-chamber bobbin, as shown here. 00:18:00.370 --> 00:18:03.540 align:middle line:84% The primary side winding and secondary side windings 00:18:03.540 --> 00:18:05.760 align:middle line:90% are put in separate chambers. 00:18:05.760 --> 00:18:08.550 align:middle line:84% They are physically separated apart. 00:18:08.550 --> 00:18:12.900 align:middle line:84% The surface area is reduced and the distance is increased. 00:18:12.900 --> 00:18:18.550 align:middle line:84% It can achieve a much smaller interwinding capacitance. 00:18:18.550 --> 00:18:21.790 align:middle line:84% Regardless of which method is used, 00:18:21.790 --> 00:18:24.970 align:middle line:84% increases in the winding distance 00:18:24.970 --> 00:18:27.790 align:middle line:84% reduces the capacitance, but it also 00:18:27.790 --> 00:18:31.660 align:middle line:84% reduces the coupling between the primary side and secondary side 00:18:31.660 --> 00:18:35.830 align:middle line:84% windings, which means the leakage inductance will also 00:18:35.830 --> 00:18:36.850 align:middle line:90% be increased. 00:18:36.850 --> 00:18:39.450 align:middle line:90% 00:18:39.450 --> 00:18:42.150 align:middle line:84% This slide summarizes different transformers 00:18:42.150 --> 00:18:43.800 align:middle line:84% with different construction methods 00:18:43.800 --> 00:18:45.390 align:middle line:90% for different topologies. 00:18:45.390 --> 00:18:47.850 align:middle line:84% With respect to the interwinding capacitance, 00:18:47.850 --> 00:18:50.130 align:middle line:84% the flyback, the half-bridge, and 00:18:50.130 --> 00:18:54.210 align:middle line:84% the full-bridge transformers have relatively large values, 00:18:54.210 --> 00:18:56.520 align:middle line:90% around 20 picofarads. 00:18:56.520 --> 00:18:59.460 align:middle line:84% The push-pull transformer uses a toroid core 00:18:59.460 --> 00:19:01.590 align:middle line:84% and has an interwinding capacitance 00:19:01.590 --> 00:19:03.930 align:middle line:90% around 10 picofarads. 00:19:03.930 --> 00:19:06.300 align:middle line:84% When the split-chamber bobbin is used 00:19:06.300 --> 00:19:08.760 align:middle line:84% the interwinding capacitance can be reduced 00:19:08.760 --> 00:19:11.220 align:middle line:90% to be less than 2 picofarads. 00:19:11.220 --> 00:19:15.120 align:middle line:84% This is an order of magnitude amplitude reduction compared 00:19:15.120 --> 00:19:17.340 align:middle line:90% with the flyback transformer. 00:19:17.340 --> 00:19:19.530 align:middle line:84% The lower interwinding capacitance 00:19:19.530 --> 00:19:25.230 align:middle line:84% means the design can easily pass the high dv/dt CMTI test. 00:19:25.230 --> 00:19:28.890 align:middle line:84% It also helps achieve noise immunity of higher 00:19:28.890 --> 00:19:31.980 align:middle line:90% than 150 volts per nanoseconds. 00:19:31.980 --> 00:19:35.400 align:middle line:84% This is better than the other transformers. 00:19:35.400 --> 00:19:38.790 align:middle line:84% Not only the reduction of parasitic capacitance, 00:19:38.790 --> 00:19:43.440 align:middle line:84% the split-chamber bobbin also allows a fully automated 00:19:43.440 --> 00:19:45.760 align:middle line:90% manufacturing process. 00:19:45.760 --> 00:19:51.180 align:middle line:84% This allows the transformer cost to be 15% to 30% lower compared 00:19:51.180 --> 00:19:53.520 align:middle line:90% with the other transformers. 00:19:53.520 --> 00:19:56.100 align:middle line:84% As we discussed earlier, the reduction 00:19:56.100 --> 00:20:00.570 align:middle line:84% of the interwinding capacitance has the penalty of increasing 00:20:00.570 --> 00:20:02.040 align:middle line:90% leakage inductance. 00:20:02.040 --> 00:20:04.710 align:middle line:84% The split-chamber bobbin transformer 00:20:04.710 --> 00:20:06.960 align:middle line:84% has a much higher leakage inductance. 00:20:06.960 --> 00:20:10.620 align:middle line:84% The push-pull transformer uses bifilar 00:20:10.620 --> 00:20:14.760 align:middle line:84% to achieve a very low leakage inductance. 00:20:14.760 --> 00:20:18.720 align:middle line:84% In terms of regulation, the PSR flyback 00:20:18.720 --> 00:20:23.160 align:middle line:84% allows the closed-loop control to achieve the best regulation 00:20:23.160 --> 00:20:24.960 align:middle line:90% performance. 00:20:24.960 --> 00:20:29.370 align:middle line:84% The three-winding flyback uses the rectified aux winding 00:20:29.370 --> 00:20:31.830 align:middle line:90% voltage as the feedback. 00:20:31.830 --> 00:20:34.380 align:middle line:84% It gets good regulation performance, 00:20:34.380 --> 00:20:39.120 align:middle line:84% but not as good as a true PSR flyback controller. 00:20:39.120 --> 00:20:43.050 align:middle line:84% The other transformers are used for open-loop control. 00:20:43.050 --> 00:20:46.635 align:middle line:84% The voltage regulation performance is not as good. 00:20:46.635 --> 00:20:50.860 align:middle line:90% 00:20:50.860 --> 00:20:52.960 align:middle line:84% To get better EMI performance, we 00:20:52.960 --> 00:20:56.050 align:middle line:84% need the buyer supply to have a minimum interwinding 00:20:56.050 --> 00:20:57.610 align:middle line:90% capacitance. 00:20:57.610 --> 00:21:02.020 align:middle line:84% As a result, the transformer will have a much larger leakage 00:21:02.020 --> 00:21:03.010 align:middle line:90% inductance. 00:21:03.010 --> 00:21:07.120 align:middle line:84% However, not every topology is able to use a transformer 00:21:07.120 --> 00:21:09.190 align:middle line:90% with large leakage inductance. 00:21:09.190 --> 00:21:12.730 align:middle line:84% For example, in flyback or push-pull converters, 00:21:12.730 --> 00:21:15.770 align:middle line:84% the transformer is in series with the switch. 00:21:15.770 --> 00:21:18.220 align:middle line:84% Once the switch turns off, the energy 00:21:18.220 --> 00:21:21.370 align:middle line:84% stored in the leakage inductance has no place to go. 00:21:21.370 --> 00:21:24.280 align:middle line:84% It can't be transferred to the secondary side. 00:21:24.280 --> 00:21:27.790 align:middle line:84% The leakage inductor resonates with the switch node capacitor, 00:21:27.790 --> 00:21:32.560 align:middle line:84% causing more EMI noise, more loss, and more voltage stress 00:21:32.560 --> 00:21:35.830 align:middle line:84% on the devices because of the voltage ringing. 00:21:35.830 --> 00:21:38.410 align:middle line:84% Furthermore, a snubber is often added 00:21:38.410 --> 00:21:40.660 align:middle line:90% to manage the leakage energy. 00:21:40.660 --> 00:21:44.030 align:middle line:84% This could also increase the solution cost. 00:21:44.030 --> 00:21:46.810 align:middle line:84% Therefore, for these topologies, the leakage 00:21:46.810 --> 00:21:50.470 align:middle line:84% has to be minimized, which means the transformer interwinding 00:21:50.470 --> 00:21:53.950 align:middle line:90% capacitances can't be reduced. 00:21:53.950 --> 00:21:56.440 align:middle line:84% In a half-bridge converter, the transformer 00:21:56.440 --> 00:21:58.450 align:middle line:90% is connected with a half bridge. 00:21:58.450 --> 00:22:02.350 align:middle line:84% The leakage energy can be fully recovered 00:22:02.350 --> 00:22:05.470 align:middle line:84% and the leakage inductor won't cause extra ringing. 00:22:05.470 --> 00:22:08.380 align:middle line:84% However, the leakage inductance still 00:22:08.380 --> 00:22:12.250 align:middle line:84% needs to be minimized for the voltage regulation. 00:22:12.250 --> 00:22:16.290 align:middle line:90% 00:22:16.290 --> 00:22:18.480 align:middle line:84% Let's take a look at the half bridge. 00:22:18.480 --> 00:22:22.200 align:middle line:84% The half-bridge converter can be used as a PWM converter 00:22:22.200 --> 00:22:24.340 align:middle line:90% or a resonant converter. 00:22:24.340 --> 00:22:26.700 align:middle line:84% When it is used as a PWM converter, 00:22:26.700 --> 00:22:29.730 align:middle line:84% the leakage inductance is between the input voltage 00:22:29.730 --> 00:22:31.410 align:middle line:90% and the output voltage. 00:22:31.410 --> 00:22:33.570 align:middle line:84% If we draw its equivalent circuit, 00:22:33.570 --> 00:22:36.990 align:middle line:84% basically the leakage inductance is in between the input 00:22:36.990 --> 00:22:38.100 align:middle line:90% and the load. 00:22:38.100 --> 00:22:42.390 align:middle line:84% For different loads, the larger leakage inductance equivalently 00:22:42.390 --> 00:22:46.500 align:middle line:84% gives more impedance to the source, which causes worse load 00:22:46.500 --> 00:22:48.300 align:middle line:90% regulation performance. 00:22:48.300 --> 00:22:50.490 align:middle line:84% In this case, the leakage inductance 00:22:50.490 --> 00:22:52.950 align:middle line:90% still needs to be minimized. 00:22:52.950 --> 00:22:55.410 align:middle line:84% However, when the half-bridge operates 00:22:55.410 --> 00:22:59.160 align:middle line:84% as a resonant converter, we put a resonant cap in series 00:22:59.160 --> 00:23:01.080 align:middle line:90% with the leakage inductance. 00:23:01.080 --> 00:23:04.660 align:middle line:84% When the switching frequency is at the resonant frequency, 00:23:04.660 --> 00:23:07.530 align:middle line:84% the resonant tank impedance is zero. 00:23:07.530 --> 00:23:11.820 align:middle line:84% It can achieve a much better load regulation performance. 00:23:11.820 --> 00:23:15.750 align:middle line:84% Because the resonant capacitor can tune out 00:23:15.750 --> 00:23:18.510 align:middle line:84% the leakage inductance impedance, 00:23:18.510 --> 00:23:21.780 align:middle line:84% transformers used in the resonant half bridge 00:23:21.780 --> 00:23:24.960 align:middle line:84% can be low capacitance and high leakage. 00:23:24.960 --> 00:23:28.930 align:middle line:90% 00:23:28.930 --> 00:23:33.670 align:middle line:84% One popular resonant half-bridge converter is the LLC converter. 00:23:33.670 --> 00:23:37.660 align:middle line:84% It gets its name from its resonant components-- 00:23:37.660 --> 00:23:40.030 align:middle line:90% L, L, and C. 00:23:40.030 --> 00:23:46.110 align:middle line:84% The two resident inductors can be part of the transformer. 00:23:46.110 --> 00:23:49.680 align:middle line:84% LR is the leakage inductance and LM is the transformer 00:23:49.680 --> 00:23:52.140 align:middle line:90% magnetizing inductance. 00:23:52.140 --> 00:23:54.450 align:middle line:84% The resonant frequency is determined 00:23:54.450 --> 00:24:00.210 align:middle line:84% by the resonant capacitor, CR, and the resonant inductor, LR. 00:24:00.210 --> 00:24:04.080 align:middle line:84% The half bridge operates with a 50% duty cycle. 00:24:04.080 --> 00:24:07.450 align:middle line:84% When it's switching frequency is at the resonant frequency, 00:24:07.450 --> 00:24:11.190 align:middle line:84% the transformer primary side and secondary side currents 00:24:11.190 --> 00:24:13.050 align:middle line:90% are both sinusoidal. 00:24:13.050 --> 00:24:16.020 align:middle line:84% There is a slight phase shift between the primary side 00:24:16.020 --> 00:24:18.690 align:middle line:84% current and secondary site current. 00:24:18.690 --> 00:24:21.240 align:middle line:84% This is caused by the magnetizing current. 00:24:21.240 --> 00:24:25.080 align:middle line:84% The secondary side current is then rectified and filtered out 00:24:25.080 --> 00:24:28.020 align:middle line:90% to create the output voltage. 00:24:28.020 --> 00:24:30.510 align:middle line:84% The voltage gain of this converter 00:24:30.510 --> 00:24:32.910 align:middle line:90% can be defined by this equation. 00:24:32.910 --> 00:24:36.670 align:middle line:84% Here, 2 comes from the half-bridge operation. 00:24:36.670 --> 00:24:39.210 align:middle line:84% The resonant frequency comes from the series, 00:24:39.210 --> 00:24:43.710 align:middle line:84% L and C. The load resistor is converted based 00:24:43.710 --> 00:24:45.720 align:middle line:90% on the sinusoidal current. 00:24:45.720 --> 00:24:48.000 align:middle line:84% And the quality factor is defined 00:24:48.000 --> 00:24:50.670 align:middle line:84% by the typical characteristic impedance 00:24:50.670 --> 00:24:54.150 align:middle line:90% divided by the equivalent load. 00:24:54.150 --> 00:24:58.560 align:middle line:84% The normalized gain curve of the LLC converter is shown here. 00:24:58.560 --> 00:25:00.660 align:middle line:84% The switching frequency is normalized 00:25:00.660 --> 00:25:02.220 align:middle line:90% with the resonant frequency. 00:25:02.220 --> 00:25:06.930 align:middle line:84% And each curve represents different load conditions. 00:25:06.930 --> 00:25:09.300 align:middle line:84% Generally, the voltage gain becomes 00:25:09.300 --> 00:25:13.150 align:middle line:84% higher when the switching frequency becomes higher. 00:25:13.150 --> 00:25:15.450 align:middle line:84% However, noticing this point, right 00:25:15.450 --> 00:25:18.750 align:middle line:84% at the resonant frequency, the gain is equal to 1, 00:25:18.750 --> 00:25:21.150 align:middle line:90% regardless of load conditions. 00:25:21.150 --> 00:25:23.910 align:middle line:90% 00:25:23.910 --> 00:25:26.440 align:middle line:84% This is because at the resonant frequency 00:25:26.440 --> 00:25:30.480 align:middle line:84% the impedance of the resonant tank is equal to zero. 00:25:30.480 --> 00:25:33.270 align:middle line:84% The input and output voltages are shorted 00:25:33.270 --> 00:25:35.020 align:middle line:90% through the transformer. 00:25:35.020 --> 00:25:40.350 align:middle line:84% This property allows us to use the converter with a fixed 00:25:40.350 --> 00:25:43.290 align:middle line:90% frequency open-loop control. 00:25:43.290 --> 00:25:47.340 align:middle line:84% With low capacitance, large leakage transformer, 00:25:47.340 --> 00:25:50.190 align:middle line:84% the leakage inductor can be conveniently used 00:25:50.190 --> 00:25:52.830 align:middle line:90% as the resonant inductor. 00:25:52.830 --> 00:25:56.040 align:middle line:84% Looking at this set of curves, gain 00:25:56.040 --> 00:25:58.530 align:middle line:84% is only the same when the switching frequency 00:25:58.530 --> 00:26:00.570 align:middle line:84% is equal to the resonant frequency. 00:26:00.570 --> 00:26:04.680 align:middle line:84% In reality, it is impossible to always achieve that. 00:26:04.680 --> 00:26:06.810 align:middle line:84% What if the switching frequency is not 00:26:06.810 --> 00:26:08.820 align:middle line:90% equal to the resonant frequency? 00:26:08.820 --> 00:26:11.000 align:middle line:90% Can we still use the topology? 00:26:11.000 --> 00:26:14.810 align:middle line:90% 00:26:14.810 --> 00:26:17.710 align:middle line:84% First, let's take a look at the LLC gain curves 00:26:17.710 --> 00:26:19.780 align:middle line:84% with different leakage indulgences. 00:26:19.780 --> 00:26:22.990 align:middle line:84% Here, we define a new parameter, LN. 00:26:22.990 --> 00:26:26.110 align:middle line:84% LN is the ratio between magnetizing inductance 00:26:26.110 --> 00:26:28.000 align:middle line:90% and the leakage inductance. 00:26:28.000 --> 00:26:30.880 align:middle line:84% Or, another way to put it, it's 1 00:26:30.880 --> 00:26:34.310 align:middle line:90% over the percentage of leakage. 00:26:34.310 --> 00:26:36.620 align:middle line:84% Here, we show two sets of curves, 00:26:36.620 --> 00:26:41.030 align:middle line:84% one with a relatively small LN equal to 1. 00:26:41.030 --> 00:26:43.190 align:middle line:84% You can see that the gain curve is 00:26:43.190 --> 00:26:46.070 align:middle line:84% very sensitive to the switching frequency. 00:26:46.070 --> 00:26:51.050 align:middle line:84% A small frequency change could result in large voltage gain 00:26:51.050 --> 00:26:52.250 align:middle line:90% changes. 00:26:52.250 --> 00:26:55.910 align:middle line:84% However, when the LN is relatively large, 00:26:55.910 --> 00:27:00.290 align:middle line:84% say equal to 15, the gain curve becomes much flatter. 00:27:00.290 --> 00:27:02.600 align:middle line:84% This means that the voltage gain is 00:27:02.600 --> 00:27:05.240 align:middle line:84% less sensitive to the frequency change. 00:27:05.240 --> 00:27:08.600 align:middle line:84% The circuit can tolerate frequency error 00:27:08.600 --> 00:27:10.880 align:middle line:90% from the component tolerances. 00:27:10.880 --> 00:27:15.080 align:middle line:84% Or, in other words, when the magnetizing inductor 00:27:15.080 --> 00:27:18.860 align:middle line:84% is much larger than the resonant inductor, 00:27:18.860 --> 00:27:23.000 align:middle line:84% around the resonant frequency the gain curve is flat. 00:27:23.000 --> 00:27:27.460 align:middle line:84% We should use the LLC converter with such a transformer. 00:27:27.460 --> 00:27:31.590 align:middle line:90% 00:27:31.590 --> 00:27:33.720 align:middle line:84% Other than circuit parameters, we 00:27:33.720 --> 00:27:36.780 align:middle line:84% can also adjust the circuit configuration 00:27:36.780 --> 00:27:40.350 align:middle line:84% to make the voltage gain less sensitive to the frequency 00:27:40.350 --> 00:27:41.400 align:middle line:90% shift. 00:27:41.400 --> 00:27:44.940 align:middle line:84% Here are shown two circuit schematics. 00:27:44.940 --> 00:27:47.980 align:middle line:90% They are almost identical. 00:27:47.980 --> 00:27:51.630 align:middle line:84% There is a slight difference between the two, the location 00:27:51.630 --> 00:27:53.940 align:middle line:90% of the resonant capacitor. 00:27:53.940 --> 00:27:57.570 align:middle line:84% The circuit on the left has its resonant capacitor 00:27:57.570 --> 00:28:02.310 align:middle line:84% located on the primary side, while the circuit on the right 00:28:02.310 --> 00:28:06.900 align:middle line:84% has its resonant capacitor located on the secondary side. 00:28:06.900 --> 00:28:10.470 align:middle line:84% When we do the gain analysis of these two converters, 00:28:10.470 --> 00:28:15.030 align:middle line:84% assuming a 24-volt input and a one-to-one transformer 00:28:15.030 --> 00:28:18.420 align:middle line:84% turns ratio for the primary-side resonant, 00:28:18.420 --> 00:28:22.920 align:middle line:84% the voltage gain changes with frequency. 00:28:22.920 --> 00:28:26.450 align:middle line:84% While for the secondary-side resonant, 00:28:26.450 --> 00:28:31.010 align:middle line:84% the voltage gain is almost flat when the switching frequency 00:28:31.010 --> 00:28:33.530 align:middle line:84% is below the resonant frequency, which 00:28:33.530 --> 00:28:37.250 align:middle line:84% means the secondary-side operation is even less 00:28:37.250 --> 00:28:40.820 align:middle line:84% sensitive to the frequency tolerances. 00:28:40.820 --> 00:28:42.170 align:middle line:90% But why? 00:28:42.170 --> 00:28:44.720 align:middle line:84% Comparing the operation waveforms, 00:28:44.720 --> 00:28:49.460 align:middle line:84% these two circuits have very similar switch node waveforms 00:28:49.460 --> 00:28:51.230 align:middle line:90% and current waveforms. 00:28:51.230 --> 00:28:55.250 align:middle line:84% When the switching frequency is below the resonant frequency, 00:28:55.250 --> 00:28:59.480 align:middle line:84% however, the difference happens during this period 00:28:59.480 --> 00:29:01.730 align:middle line:90% when the resonance stops. 00:29:01.730 --> 00:29:05.540 align:middle line:84% For the primary-side resonant circuit, during this period, 00:29:05.540 --> 00:29:08.630 align:middle line:84% the secondary-side circuit is off. 00:29:08.630 --> 00:29:11.990 align:middle line:84% The magnetizing inductor will resonate 00:29:11.990 --> 00:29:16.370 align:middle line:84% with the resonant capacitor and transfer its energy 00:29:16.370 --> 00:29:18.320 align:middle line:90% to the resonant capacitor. 00:29:18.320 --> 00:29:21.810 align:middle line:84% In the next half-switching cycle, 00:29:21.810 --> 00:29:25.290 align:middle line:84% the energy is transferred to the secondary side. 00:29:25.290 --> 00:29:29.430 align:middle line:84% This causes the gain to become higher. 00:29:29.430 --> 00:29:31.890 align:middle line:84% For the secondary-side resonant circuit, 00:29:31.890 --> 00:29:35.910 align:middle line:84% at the same period, because the resonant cap is located 00:29:35.910 --> 00:29:38.400 align:middle line:84% on the secondary side, the energy 00:29:38.400 --> 00:29:40.650 align:middle line:84% stored in the magnetizing inductor 00:29:40.650 --> 00:29:46.150 align:middle line:84% is fed back to the source, but not to the secondary side. 00:29:46.150 --> 00:29:49.440 align:middle line:84% This means the voltage gain won't go up. 00:29:49.440 --> 00:29:52.360 align:middle line:84% Once the operation principle is clear, 00:29:52.360 --> 00:29:56.130 align:middle line:84% we can see that the secondary-side resonant circuit 00:29:56.130 --> 00:29:59.685 align:middle line:84% is less sensitive to the switching frequency errors. 00:29:59.685 --> 00:30:02.560 align:middle line:90% 00:30:02.560 --> 00:30:07.330 align:middle line:84% There are a few variations of the half-bridge LLC converter-- 00:30:07.330 --> 00:30:11.270 align:middle line:84% through the transformer, the rectification method, 00:30:11.270 --> 00:30:14.620 align:middle line:84% as well as the resonant capacitor location. 00:30:14.620 --> 00:30:18.010 align:middle line:84% Regardless which configuration we choose, 00:30:18.010 --> 00:30:21.310 align:middle line:84% the filter cap should always be much larger 00:30:21.310 --> 00:30:24.610 align:middle line:84% than the resonant cap to prevent its interaction 00:30:24.610 --> 00:30:26.440 align:middle line:90% with the resonance. 00:30:26.440 --> 00:30:29.650 align:middle line:84% The transformer can use two simple windings 00:30:29.650 --> 00:30:32.080 align:middle line:90% or a center-tap structure. 00:30:32.080 --> 00:30:35.290 align:middle line:84% Since the LLC converter uses a capacitive filter 00:30:35.290 --> 00:30:38.590 align:middle line:84% at its output, the same as a flyback converter, 00:30:38.590 --> 00:30:41.590 align:middle line:84% it can also be used with multiple secondary-side 00:30:41.590 --> 00:30:45.570 align:middle line:84% windings to create multiple output voltages. 00:30:45.570 --> 00:30:50.460 align:middle line:84% The rectification method, we can use the full-bridge rectifier 00:30:50.460 --> 00:30:53.520 align:middle line:84% as shown in the original circuit or use 00:30:53.520 --> 00:30:56.940 align:middle line:84% the center tap with the center-tap transformer. 00:30:56.940 --> 00:30:59.580 align:middle line:84% We can use the voltage doubler structure 00:30:59.580 --> 00:31:01.980 align:middle line:90% with one or two capacitors. 00:31:01.980 --> 00:31:06.090 align:middle line:84% The one capacitor is basically those two capacitors 00:31:06.090 --> 00:31:07.560 align:middle line:90% in parallel. 00:31:07.560 --> 00:31:11.610 align:middle line:84% At low power levels, there is really not much difference 00:31:11.610 --> 00:31:13.830 align:middle line:90% between these two structures. 00:31:13.830 --> 00:31:19.740 align:middle line:84% You can pick up one based on the size and cost considerations. 00:31:19.740 --> 00:31:23.340 align:middle line:84% The resonant cap location has been discussed 00:31:23.340 --> 00:31:25.380 align:middle line:90% in the previous slide. 00:31:25.380 --> 00:31:30.900 align:middle line:84% Considering all these options, the two-winding transformer, 00:31:30.900 --> 00:31:34.740 align:middle line:84% voltage doubler, and the secondary-side resonant 00:31:34.740 --> 00:31:37.830 align:middle line:90% could be a preferred solution. 00:31:37.830 --> 00:31:42.180 align:middle line:84% The voltage doubler also brings an additional benefit. 00:31:42.180 --> 00:31:46.590 align:middle line:84% Because of the half bridge, the transformer primary only 00:31:46.590 --> 00:31:49.770 align:middle line:90% sees half of the input voltage. 00:31:49.770 --> 00:31:51.900 align:middle line:84% When the voltage doubler is used, 00:31:51.900 --> 00:31:55.050 align:middle line:84% the transformer secondary side only 00:31:55.050 --> 00:31:57.460 align:middle line:90% sees half of the output voltage. 00:31:57.460 --> 00:32:02.280 align:middle line:84% This means the voltage conversion ratio is simply 00:32:02.280 --> 00:32:04.980 align:middle line:90% the transformer turns ratio. 00:32:04.980 --> 00:32:07.140 align:middle line:90% This makes the math easier. 00:32:07.140 --> 00:32:10.830 align:middle line:90% 00:32:10.830 --> 00:32:13.710 align:middle line:84% The voltage gain analysis done so far 00:32:13.710 --> 00:32:16.360 align:middle line:84% is based on the ideal conditions. 00:32:16.360 --> 00:32:19.470 align:middle line:84% The open-loop LLC voltage regulation 00:32:19.470 --> 00:32:23.310 align:middle line:84% can be calculated considering all the lossy elements 00:32:23.310 --> 00:32:24.780 align:middle line:90% in the circuit. 00:32:24.780 --> 00:32:28.410 align:middle line:84% Here, I show a half-bridge LLC resonant converter 00:32:28.410 --> 00:32:31.500 align:middle line:84% with a voltage doubler output stage. 00:32:31.500 --> 00:32:33.960 align:middle line:84% When we consider the losses, the circuit 00:32:33.960 --> 00:32:36.240 align:middle line:90% can be redrawn like this. 00:32:36.240 --> 00:32:39.180 align:middle line:84% The switch is replaced by an ideal switch 00:32:39.180 --> 00:32:41.520 align:middle line:90% with its on-state resistance. 00:32:41.520 --> 00:32:45.540 align:middle line:84% RP represents the transformer primary-side resistance. 00:32:45.540 --> 00:32:48.030 align:middle line:84% And RS represents the transformer 00:32:48.030 --> 00:32:53.400 align:middle line:84% secondary-side resistance and other resistive conduction 00:32:53.400 --> 00:32:56.790 align:middle line:84% losses from the capacitor and diode. 00:32:56.790 --> 00:32:59.550 align:middle line:84% Because the primary side is a half bridge, 00:32:59.550 --> 00:33:03.460 align:middle line:84% we can represent the input voltage as a square wave. 00:33:03.460 --> 00:33:05.850 align:middle line:84% Same thing for the secondary side-- 00:33:05.850 --> 00:33:09.720 align:middle line:84% represent the secondary side using a square wave. 00:33:09.720 --> 00:33:13.590 align:middle line:84% At the same time, we can reflect everything from the primary 00:33:13.590 --> 00:33:17.340 align:middle line:84% to the secondary side to simplify the math. 00:33:17.340 --> 00:33:20.790 align:middle line:84% The square wave is still quite difficult to analyze, 00:33:20.790 --> 00:33:24.870 align:middle line:84% given the circuit operates very close to the resonant frequency 00:33:24.870 --> 00:33:29.640 align:middle line:84% and the resonant tank impedance increases rapidly 00:33:29.640 --> 00:33:33.420 align:middle line:84% when the frequency moves away from the resonant frequency. 00:33:33.420 --> 00:33:38.190 align:middle line:84% Basically, only the fundamental harmonic of the square wave 00:33:38.190 --> 00:33:40.770 align:middle line:84% can be transferred through the circuit. 00:33:40.770 --> 00:33:44.610 align:middle line:84% We can replace the square wave with its fundamental frequency 00:33:44.610 --> 00:33:48.270 align:middle line:84% component and represent the output with an equivalent 00:33:48.270 --> 00:33:51.670 align:middle line:84% resistor, and the circuit becomes this. 00:33:51.670 --> 00:33:54.360 align:middle line:84% Now the circuit can be analyzed easily 00:33:54.360 --> 00:33:57.930 align:middle line:84% and the output voltage can be written in this equation. 00:33:57.930 --> 00:33:59.550 align:middle line:90% It has two terms-- 00:33:59.550 --> 00:34:02.650 align:middle line:90% a DC voltage and an impedance. 00:34:02.650 --> 00:34:06.120 align:middle line:84% So the output behaves as a DC source 00:34:06.120 --> 00:34:09.810 align:middle line:90% with finite internal impedance. 00:34:09.810 --> 00:34:14.889 align:middle line:84% The DC voltage is the input voltage 00:34:14.889 --> 00:34:19.659 align:middle line:84% reflected to the secondary side, then minus the diode drop. 00:34:19.659 --> 00:34:23.389 align:middle line:84% The impedance represents the circuit loss. 00:34:23.389 --> 00:34:26.780 align:middle line:84% It's the combination of the switch on-state resistance, 00:34:26.780 --> 00:34:29.449 align:middle line:84% the AC resistance from the transformer, 00:34:29.449 --> 00:34:33.800 align:middle line:84% and the resistive loss from the capacitor and the diode. 00:34:33.800 --> 00:34:36.620 align:middle line:84% When using the closed-loop control, 00:34:36.620 --> 00:34:40.040 align:middle line:84% the internal impedance can be tuned out. 00:34:40.040 --> 00:34:42.679 align:middle line:84% When using the open-loop control, 00:34:42.679 --> 00:34:44.840 align:middle line:84% we have to live with this impedance. 00:34:44.840 --> 00:34:47.600 align:middle line:84% We can try to minimize the resistive loss 00:34:47.600 --> 00:34:51.370 align:middle line:84% to get lower output impedance and better load regulation. 00:34:51.370 --> 00:34:54.630 align:middle line:90% 00:34:54.630 --> 00:34:57.240 align:middle line:84% Even though the open-loop LLC output 00:34:57.240 --> 00:35:00.690 align:middle line:84% can see some load regulation, the load regulation 00:35:00.690 --> 00:35:03.900 align:middle line:84% behaves differently for different load conditions. 00:35:03.900 --> 00:35:07.290 align:middle line:84% This plot shows a curve that represents a typical output 00:35:07.290 --> 00:35:10.110 align:middle line:84% voltage at different load conditions. 00:35:10.110 --> 00:35:13.680 align:middle line:84% When the load increases, the output voltage drops. 00:35:13.680 --> 00:35:16.350 align:middle line:84% When we make a large number of these circuits 00:35:16.350 --> 00:35:19.170 align:middle line:84% due to component tolerances, the output voltage 00:35:19.170 --> 00:35:20.880 align:middle line:90% will be within these bands. 00:35:20.880 --> 00:35:23.790 align:middle line:84% Some will be higher and some will be lower. 00:35:23.790 --> 00:35:26.820 align:middle line:84% As we discussed earlier, the gate-drive power 00:35:26.820 --> 00:35:30.660 align:middle line:84% is determined by the driver voltage, gate charge, 00:35:30.660 --> 00:35:32.490 align:middle line:90% and the switching frequency. 00:35:32.490 --> 00:35:36.180 align:middle line:84% Given the driver voltage and gate charges fixed, 00:35:36.180 --> 00:35:40.140 align:middle line:84% the load is only determined by the switching frequency. 00:35:40.140 --> 00:35:43.350 align:middle line:84% For a fixed switching frequency inverter, 00:35:43.350 --> 00:35:46.920 align:middle line:84% the gate-drive power is fixed and the output voltage 00:35:46.920 --> 00:35:49.050 align:middle line:90% varies from here to here. 00:35:49.050 --> 00:35:52.470 align:middle line:84% It is much smaller compared with the entire load 00:35:52.470 --> 00:35:54.390 align:middle line:90% range and tolerances. 00:35:54.390 --> 00:35:58.380 align:middle line:84% The voltage regulation can be very tight. 00:35:58.380 --> 00:36:04.160 align:middle line:84% During standby mode, the gate-drive losses 00:36:04.160 --> 00:36:06.200 align:middle line:90% become a minimum. 00:36:06.200 --> 00:36:08.690 align:middle line:84% The output voltage tends to go higher 00:36:08.690 --> 00:36:11.420 align:middle line:84% due to the junction capacitance of the diode 00:36:11.420 --> 00:36:13.070 align:middle line:90% in the bias supply. 00:36:13.070 --> 00:36:16.190 align:middle line:84% An additional dummy load or Zener clamp 00:36:16.190 --> 00:36:20.990 align:middle line:84% might be needed to prevent that voltage from becoming too high. 00:36:20.990 --> 00:36:23.480 align:middle line:84% For a variable frequency inverter, 00:36:23.480 --> 00:36:27.950 align:middle line:84% the gate-drive load varies and the output voltage varies more. 00:36:27.950 --> 00:36:32.820 align:middle line:90% 00:36:32.820 --> 00:36:36.220 align:middle line:84% The best way to analyze the output voltage regulation, 00:36:36.220 --> 00:36:38.680 align:middle line:84% considering the component tolerances, 00:36:38.680 --> 00:36:42.790 align:middle line:84% would be to use a Monte Carlo simulation. 00:36:42.790 --> 00:36:46.990 align:middle line:84% This circuit is used to simulate the output voltage tolerances. 00:36:46.990 --> 00:36:49.270 align:middle line:90% Here are some assumptions. 00:36:49.270 --> 00:36:52.570 align:middle line:84% We'll use a 24-volt input with the transformer turns 00:36:52.570 --> 00:36:55.570 align:middle line:90% ratio assumed to be one-to-one. 00:36:55.570 --> 00:36:57.580 align:middle line:84% The leakage inductance is distributed 00:36:57.580 --> 00:37:00.790 align:middle line:84% evenly on the primary side and secondary side 00:37:00.790 --> 00:37:03.220 align:middle line:90% with a 20% tolerance. 00:37:03.220 --> 00:37:05.590 align:middle line:84% The tolerance of the magnetizing inductor 00:37:05.590 --> 00:37:10.300 align:middle line:84% is 40%, 6% switching frequency tolerance, 00:37:10.300 --> 00:37:14.140 align:middle line:84% and 10% tolerance for the resonant capacitor. 00:37:14.140 --> 00:37:17.530 align:middle line:84% With all these tolerances, for each load condition, 00:37:17.530 --> 00:37:22.330 align:middle line:84% we can see the output voltage varies about 0.2 volts 00:37:22.330 --> 00:37:24.310 align:middle line:90% at a 22-volt output. 00:37:24.310 --> 00:37:27.130 align:middle line:84% This shows the output voltage is really not 00:37:27.130 --> 00:37:30.145 align:middle line:84% that sensitive to the circuit parameter shifts. 00:37:30.145 --> 00:37:33.240 align:middle line:90% 00:37:33.240 --> 00:37:36.750 align:middle line:84% Next, let's take a look at how to design this open-loop LLC 00:37:36.750 --> 00:37:37.620 align:middle line:90% converter. 00:37:37.620 --> 00:37:41.520 align:middle line:84% Traditionally, the LLC converter's design 00:37:41.520 --> 00:37:43.570 align:middle line:90% is complicated and challenging. 00:37:43.570 --> 00:37:45.510 align:middle line:84% This is because people try to optimize 00:37:45.510 --> 00:37:49.050 align:middle line:84% the efficiency, the power density, the input and output 00:37:49.050 --> 00:37:50.820 align:middle line:90% voltage range, et cetera. 00:37:50.820 --> 00:37:53.700 align:middle line:84% It is quite different in the isolated bias supply. 00:37:53.700 --> 00:37:57.090 align:middle line:84% The bias supply is a small portion of a large system. 00:37:57.090 --> 00:38:00.570 align:middle line:84% The efficiency is not critical because the loss is negligible 00:38:00.570 --> 00:38:03.090 align:middle line:84% compared with the overall system losses. 00:38:03.090 --> 00:38:06.270 align:middle line:84% Optimizing the efficiency can't improve the overall system 00:38:06.270 --> 00:38:07.350 align:middle line:90% performance. 00:38:07.350 --> 00:38:09.270 align:middle line:84% The size of the converter is normally 00:38:09.270 --> 00:38:11.970 align:middle line:84% dominated by the isolation requirement. 00:38:11.970 --> 00:38:13.950 align:middle line:84% The size reduction is mainly achieved 00:38:13.950 --> 00:38:16.770 align:middle line:84% through the minimization of the number of components 00:38:16.770 --> 00:38:19.540 align:middle line:84% instead of reducing the component size. 00:38:19.540 --> 00:38:22.500 align:middle line:84% Furthermore, because of the open-loop control, 00:38:22.500 --> 00:38:25.890 align:middle line:84% there is no need to consider voltage gain. 00:38:25.890 --> 00:38:29.730 align:middle line:84% The design of this LLC converter can be much simpler. 00:38:29.730 --> 00:38:32.790 align:middle line:84% First, based on the input voltage and output voltage 00:38:32.790 --> 00:38:34.650 align:middle line:84% requirement, the transformer turns 00:38:34.650 --> 00:38:38.040 align:middle line:84% ratio can be determined by considering 00:38:38.040 --> 00:38:39.790 align:middle line:90% the extra headroom needed. 00:38:39.790 --> 00:38:43.110 align:middle line:84% Once the transformer turns ratio is determined, with the load 00:38:43.110 --> 00:38:45.600 align:middle line:84% current requirement, the transformer primary 00:38:45.600 --> 00:38:49.510 align:middle line:84% and secondary-side RMS currents can be calculated. 00:38:49.510 --> 00:38:52.680 align:middle line:84% The input voltage, together with the switching frequency, 00:38:52.680 --> 00:38:56.340 align:middle line:84% can determine the volt second rating of the transformer. 00:38:56.340 --> 00:39:00.720 align:middle line:84% Using a split-chamber bobbin without an air gap, 00:39:00.720 --> 00:39:03.570 align:middle line:84% the transformer can be designed to achieve the desired 00:39:03.570 --> 00:39:05.400 align:middle line:90% magnetizing inductance. 00:39:05.400 --> 00:39:09.360 align:middle line:84% In this equation, the magnetizing inductance design 00:39:09.360 --> 00:39:12.000 align:middle line:84% target is to achieve soft switching. 00:39:12.000 --> 00:39:14.640 align:middle line:84% However, for this low-voltage input converter, 00:39:14.640 --> 00:39:17.670 align:middle line:84% soft switching is really not that critical. 00:39:17.670 --> 00:39:21.480 align:middle line:84% Even without ZVS, the switching loss is still small. 00:39:21.480 --> 00:39:25.800 align:middle line:84% This value gives a design target to start with. 00:39:25.800 --> 00:39:29.580 align:middle line:84% We are not giving a leakage inductance design target. 00:39:29.580 --> 00:39:32.580 align:middle line:84% Instead, once the transformer is designed, 00:39:32.580 --> 00:39:34.440 align:middle line:84% we measure the leakage inductance, 00:39:34.440 --> 00:39:36.330 align:middle line:84% then match the leakage inductance 00:39:36.330 --> 00:39:40.620 align:middle line:84% with a resonant capacitor, set up the resonant frequency 00:39:40.620 --> 00:39:43.680 align:middle line:84% at about 10% above the switching frequency. 00:39:43.680 --> 00:39:46.750 align:middle line:90% 00:39:46.750 --> 00:39:50.800 align:middle line:84% The open-loop LLC converter can give a single output voltage 00:39:50.800 --> 00:39:53.050 align:middle line:90% for the isolated gate drivers. 00:39:53.050 --> 00:39:56.500 align:middle line:84% Often positive and negative rails are needed. 00:39:56.500 --> 00:39:59.650 align:middle line:84% We can use some simple circuits to split the single output 00:39:59.650 --> 00:40:02.800 align:middle line:84% voltage into positive and negative rails. 00:40:02.800 --> 00:40:05.350 align:middle line:84% The Zener split is a simple solution. 00:40:05.350 --> 00:40:08.920 align:middle line:84% It uses a Zener diode to create the negative voltage. 00:40:08.920 --> 00:40:12.040 align:middle line:84% And the rest of the voltage becomes the positive rail. 00:40:12.040 --> 00:40:15.050 align:middle line:84% Clearly, this gives a low-cost solution. 00:40:15.050 --> 00:40:19.660 align:middle line:84% However, both the positive and negative rails are unregulated. 00:40:19.660 --> 00:40:22.840 align:middle line:84% The Zener diode can also be put on top 00:40:22.840 --> 00:40:26.680 align:middle line:84% to create the positive rail and let the remaining voltage 00:40:26.680 --> 00:40:28.180 align:middle line:90% become the negative rail. 00:40:28.180 --> 00:40:31.300 align:middle line:84% To improve the accuracy, a shunt regulator 00:40:31.300 --> 00:40:33.730 align:middle line:84% can be used to replace the Zener. 00:40:33.730 --> 00:40:36.760 align:middle line:84% This requires a higher cost, but the negative rail 00:40:36.760 --> 00:40:38.350 align:middle line:90% becomes regulated. 00:40:38.350 --> 00:40:40.930 align:middle line:84% The positive rail is still unregulated. 00:40:40.930 --> 00:40:44.140 align:middle line:84% One step further, we can add a linear regulator 00:40:44.140 --> 00:40:45.730 align:middle line:90% on the positive rail. 00:40:45.730 --> 00:40:48.580 align:middle line:84% This allows us to have a regulated positive 00:40:48.580 --> 00:40:50.980 align:middle line:90% rail and negative rail. 00:40:50.980 --> 00:40:54.700 align:middle line:84% But it requires extra cost and less efficiency. 00:40:54.700 --> 00:40:58.450 align:middle line:90% 00:40:58.450 --> 00:41:04.630 align:middle line:84% Based on all these analyses, the UCC25800-Q1 open-loop LLC 00:41:04.630 --> 00:41:06.760 align:middle line:84% transformer driver was developed. 00:41:06.760 --> 00:41:09.070 align:middle line:84% It integrates a half-bridge power stage 00:41:09.070 --> 00:41:12.910 align:middle line:84% with a 1-amp peak current capability, a frequency setting 00:41:12.910 --> 00:41:17.020 align:middle line:84% resistor to set the switching frequency between 100 kilohertz 00:41:17.020 --> 00:41:18.280 align:middle line:90% to 1 megahertz. 00:41:18.280 --> 00:41:21.070 align:middle line:84% The switching frequency becomes 1.2 megahertz 00:41:21.070 --> 00:41:22.720 align:middle line:90% if the pin is left open. 00:41:22.720 --> 00:41:27.280 align:middle line:84% It also has a built-in soft start of 1.5 milliseconds. 00:41:27.280 --> 00:41:30.070 align:middle line:84% The overcurrent protection and maximum dead time 00:41:30.070 --> 00:41:31.870 align:middle line:90% can be set up through this pin. 00:41:31.870 --> 00:41:34.990 align:middle line:84% The overcurrent level can be programmed for different power 00:41:34.990 --> 00:41:38.920 align:middle line:84% levels with overload and short-circuit protections. 00:41:38.920 --> 00:41:42.040 align:middle line:84% The maximum dead time is programmed through the divider 00:41:42.040 --> 00:41:43.060 align:middle line:90% ratio. 00:41:43.060 --> 00:41:45.970 align:middle line:84% The IC can achieve automatic dead time adjustment 00:41:45.970 --> 00:41:48.670 align:middle line:84% within the programmed maximum dead time 00:41:48.670 --> 00:41:52.540 align:middle line:84% to achieve the best ZVS performance. 00:41:52.540 --> 00:41:55.510 align:middle line:84% The IC also has a disable pin, allowing 00:41:55.510 --> 00:41:58.060 align:middle line:84% it to be disabled through an external signal. 00:41:58.060 --> 00:42:01.990 align:middle line:84% This pin also serves as a fault code output pin. 00:42:01.990 --> 00:42:04.570 align:middle line:84% It sends out a series of pulses to let 00:42:04.570 --> 00:42:07.900 align:middle line:84% the system know what protection feature is triggered. 00:42:07.900 --> 00:42:10.900 align:middle line:84% You can read the pulse number to help 00:42:10.900 --> 00:42:13.390 align:middle line:84% identify the cause of the protection 00:42:13.390 --> 00:42:16.030 align:middle line:84% and simplify the debugging process. 00:42:16.030 --> 00:42:18.760 align:middle line:84% Other than the program switching frequency, 00:42:18.760 --> 00:42:23.530 align:middle line:84% it can also be synchronized with an external clock signal. 00:42:23.530 --> 00:42:25.840 align:middle line:84% A special handoff mechanism was designed 00:42:25.840 --> 00:42:28.090 align:middle line:90% to ensure smooth transition. 00:42:28.090 --> 00:42:31.390 align:middle line:84% Here shows the transition and the circuit operation 00:42:31.390 --> 00:42:34.510 align:middle line:84% is not disturbed during the frequency handoff. 00:42:34.510 --> 00:42:39.310 align:middle line:84% It also has a full set of protection features integrated 00:42:39.310 --> 00:42:42.730 align:middle line:84% inside, including input overvoltage 00:42:42.730 --> 00:42:47.650 align:middle line:84% protection, thermal shutdown, and pin open-short protections. 00:42:47.650 --> 00:42:50.970 align:middle line:90% 00:42:50.970 --> 00:42:52.950 align:middle line:90% Here is some measure data. 00:42:52.950 --> 00:42:59.460 align:middle line:84% The measurements are based on the UCC25800 open-loop LLC EVM 00:42:59.460 --> 00:43:07.110 align:middle line:84% with the LM5156 SEPIC pre-regulator. 00:43:07.110 --> 00:43:11.670 align:middle line:84% The SEPIC circuit takes a 6 to 26-volt input voltage, 00:43:11.670 --> 00:43:15.540 align:middle line:84% converts it to a regulated 15-volt intermediate bus. 00:43:15.540 --> 00:43:21.060 align:middle line:84% Then the open-loop LLC converts the 15, plus 18 volts 00:43:21.060 --> 00:43:25.620 align:middle line:84% and minus 5 volts, with 85 milliamps of output current. 00:43:25.620 --> 00:43:29.130 align:middle line:84% The SEPIC switching frequency is at 2.2 megahertz 00:43:29.130 --> 00:43:33.770 align:middle line:84% and the LLC switching frequency is 500 kilohertz. 00:43:33.770 --> 00:43:36.620 align:middle line:84% A post-regulator circuit using a shunt regulator 00:43:36.620 --> 00:43:40.040 align:middle line:84% and a linear regulator is implemented on this board. 00:43:40.040 --> 00:43:43.520 align:middle line:84% Before, the post-regulator, the total output voltage 00:43:43.520 --> 00:43:47.360 align:middle line:84% varies between 24 volts and 25 volts. 00:43:47.360 --> 00:43:52.400 align:middle line:84% With the post-regulator, 1% load regulation can be achieved. 00:43:52.400 --> 00:43:55.580 align:middle line:84% With soft switching sinusoidal current and low 00:43:55.580 --> 00:43:58.400 align:middle line:84% interwinding capacitance, the circuit 00:43:58.400 --> 00:44:02.750 align:middle line:84% can easily pass the CISPR 25, Class 5 EMI standard. 00:44:02.750 --> 00:44:06.400 align:middle line:90% 00:44:06.400 --> 00:44:08.920 align:middle line:84% The open-loop LLC can also be used 00:44:08.920 --> 00:44:12.880 align:middle line:84% for creating multiple outputs for centralized architectures. 00:44:12.880 --> 00:44:15.580 align:middle line:84% There are two ways of creating multiple outputs-- 00:44:15.580 --> 00:44:18.340 align:middle line:84% using a transformer with multiple secondary-side 00:44:18.340 --> 00:44:23.630 align:middle line:84% windings or using a half bridge to drive multiple transformers. 00:44:23.630 --> 00:44:25.820 align:middle line:84% For the multiple secondary-side windings, 00:44:25.820 --> 00:44:27.920 align:middle line:90% only one transformer is needed. 00:44:27.920 --> 00:44:32.510 align:middle line:84% However, due to the complex coupling on the secondary side, 00:44:32.510 --> 00:44:35.090 align:middle line:90% primary resonant is preferred. 00:44:35.090 --> 00:44:38.240 align:middle line:84% In this configuration, even though we still 00:44:38.240 --> 00:44:40.940 align:middle line:84% reduce the coupling between the primary side 00:44:40.940 --> 00:44:42.470 align:middle line:90% and the secondary side. 00:44:42.470 --> 00:44:46.040 align:middle line:84% The secondary-side windings need to be coupled well. 00:44:46.040 --> 00:44:48.170 align:middle line:84% This still has the noise coupling 00:44:48.170 --> 00:44:50.930 align:middle line:90% among different outputs. 00:44:50.930 --> 00:44:55.760 align:middle line:84% Or, we can use one half bridge to drive multiple transformers. 00:44:55.760 --> 00:44:59.150 align:middle line:84% In this case, the half bridge only creates a square wave. 00:44:59.150 --> 00:45:01.850 align:middle line:84% And each LLC operates independently. 00:45:01.850 --> 00:45:04.970 align:middle line:84% The secondary-side resonant can be used. 00:45:04.970 --> 00:45:11.130 align:middle line:84% And the coupling, among all the outputs, is minimized. 00:45:11.130 --> 00:45:14.330 align:middle line:84% This is an example of using multiple transformer. 00:45:14.330 --> 00:45:19.250 align:middle line:84% The primary side is using the UCC25800 power stage. 00:45:19.250 --> 00:45:23.270 align:middle line:84% It drives three transformers and secondary-side circuits. 00:45:23.270 --> 00:45:28.490 align:middle line:84% The three output voltages are measured with 25 volts input. 00:45:28.490 --> 00:45:31.670 align:middle line:84% Three well-matched output voltages are created. 00:45:31.670 --> 00:45:34.850 align:middle line:90% 00:45:34.850 --> 00:45:37.220 align:middle line:84% The LLC converter has soft switching, 00:45:37.220 --> 00:45:43.070 align:middle line:84% lower dv/dt on the switch node, sinusoidally shaped current, 00:45:43.070 --> 00:45:45.860 align:middle line:84% and minimum interwinding capacitance. 00:45:45.860 --> 00:45:49.970 align:middle line:84% We are expecting it to have a better EMI performance 00:45:49.970 --> 00:45:54.620 align:middle line:84% all on its own, not to mention a much smaller noise coupling 00:45:54.620 --> 00:45:57.560 align:middle line:90% from the inverter power stage. 00:45:57.560 --> 00:46:00.800 align:middle line:84% Here shows the EMI performance comparisons 00:46:00.800 --> 00:46:05.180 align:middle line:84% among 5-volt input, push-pull, 24-volt input 00:46:05.180 --> 00:46:11.720 align:middle line:84% flyback, a 24-volt input LLC, without adding the EMI filter, 00:46:11.720 --> 00:46:14.030 align:middle line:90% just to see the bare noise. 00:46:14.030 --> 00:46:19.070 align:middle line:84% It can be seen that the LLC converter has a much 00:46:19.070 --> 00:46:22.750 align:middle line:90% lower high frequency EMI noise. 00:46:22.750 --> 00:46:26.860 align:middle line:84% Normally, the low frequency EMI can be handled easily 00:46:26.860 --> 00:46:28.420 align:middle line:90% through the EMI filter. 00:46:28.420 --> 00:46:31.420 align:middle line:84% But the high frequency EMI noise is much more 00:46:31.420 --> 00:46:33.100 align:middle line:90% difficult to manage. 00:46:33.100 --> 00:46:37.450 align:middle line:84% The LLC converter provides a much better EMI noise 00:46:37.450 --> 00:46:38.170 align:middle line:90% performance. 00:46:38.170 --> 00:46:41.850 align:middle line:90% 00:46:41.850 --> 00:46:47.320 align:middle line:84% We also put the circuit into a CMTI test. 00:46:47.320 --> 00:46:51.670 align:middle line:84% CMTI stands for Common Mode Transient Immunity. 00:46:51.670 --> 00:46:54.760 align:middle line:84% As we discussed earlier, when the bias supply is 00:46:54.760 --> 00:46:57.700 align:middle line:84% used to power the high-side gate driver, 00:46:57.700 --> 00:47:00.970 align:middle line:84% the high dv/dt from the inverter power stage 00:47:00.970 --> 00:47:04.240 align:middle line:84% can be coupled through the transformer interwinding 00:47:04.240 --> 00:47:07.300 align:middle line:84% capacitor to cause common-mode current 00:47:07.300 --> 00:47:09.040 align:middle line:90% and cause different issues. 00:47:09.040 --> 00:47:13.600 align:middle line:84% This dv/dt can be well above 50 volts per nanosecond. 00:47:13.600 --> 00:47:16.360 align:middle line:84% This condition can be simulated by adding 00:47:16.360 --> 00:47:20.590 align:middle line:84% a pulse voltage between the bias supply input and the output 00:47:20.590 --> 00:47:21.610 align:middle line:90% grounds. 00:47:21.610 --> 00:47:24.640 align:middle line:84% We call this voltage a strike voltage. 00:47:24.640 --> 00:47:28.670 align:middle line:90% 00:47:28.670 --> 00:47:31.930 align:middle line:84% This slide shows the CMTI performance. 00:47:31.930 --> 00:47:35.290 align:middle line:84% The blue waveform is the LLC switch node voltage. 00:47:35.290 --> 00:47:38.440 align:middle line:84% And the yellow curve is the strike voltage. 00:47:38.440 --> 00:47:40.870 align:middle line:84% Looking into the details, we can see 00:47:40.870 --> 00:47:44.350 align:middle line:84% the strike voltage has a slew rate of 165 00:47:44.350 --> 00:47:47.290 align:middle line:84% volts per nanosecond at its rising edge, 00:47:47.290 --> 00:47:52.270 align:middle line:84% and 155 volts per nanosecond slew rate at its falling edge. 00:47:52.270 --> 00:47:58.150 align:middle line:84% The strike voltage is from negative 500 to plus-500 volts. 00:47:58.150 --> 00:48:01.450 align:middle line:84% Looking at the LLC switch node behavior, right 00:48:01.450 --> 00:48:05.890 align:middle line:84% around the strike edge we can see with the higher 00:48:05.890 --> 00:48:09.460 align:middle line:84% than 150 volt per nanosecond voltage slew rate, 00:48:09.460 --> 00:48:13.270 align:middle line:84% the LLC converter operation is not disturbed. 00:48:13.270 --> 00:48:17.620 align:middle line:84% The circuit can withstand this high dv/dt easily. 00:48:17.620 --> 00:48:21.260 align:middle line:90% 00:48:21.260 --> 00:48:23.950 align:middle line:84% Other than the EVM, there are some reference 00:48:23.950 --> 00:48:27.940 align:middle line:84% designs available to assist your design. 00:48:27.940 --> 00:48:35.680 align:middle line:84% The PMP22835 is a 24 volt in, 18 volt, and minus-5 volt output, 00:48:35.680 --> 00:48:38.530 align:middle line:90% 6 watt, 1 megahertz design. 00:48:38.530 --> 00:48:43.480 align:middle line:84% The PMP22930 takes 15 volts in, creates 00:48:43.480 --> 00:48:49.270 align:middle line:84% a plus-15 and minus-4 volt, 2.6 watt output with a 600 00:48:49.270 --> 00:48:51.850 align:middle line:90% kilohertz switching frequency. 00:48:51.850 --> 00:48:57.850 align:middle line:84% The PMP23061 has a boost regulator that regulates a 6 00:48:57.850 --> 00:49:02.050 align:middle line:84% to 28-volt input voltage to a 30-volt intermediate bus 00:49:02.050 --> 00:49:03.310 align:middle line:90% voltage. 00:49:03.310 --> 00:49:09.850 align:middle line:84% One UCC25800 then converts it to four 18-volt outputs, 00:49:09.850 --> 00:49:13.490 align:middle line:84% one 3-watt output, and three 1-watt outputs. 00:49:13.490 --> 00:49:16.510 align:middle line:84% It has 500 kilohertz switching frequency. 00:49:16.510 --> 00:49:20.570 align:middle line:84% This is designed to power up three-phase inverter gate 00:49:20.570 --> 00:49:21.070 align:middle line:90% drivers. 00:49:21.070 --> 00:49:24.750 align:middle line:90% 00:49:24.750 --> 00:49:29.180 align:middle line:84% Here's a summary of what we discussed in this presentation. 00:49:29.180 --> 00:49:32.390 align:middle line:84% An isolated bias supply is necessary for the biasing 00:49:32.390 --> 00:49:35.660 align:middle line:84% of isolated gate drivers in inverters. 00:49:35.660 --> 00:49:39.050 align:middle line:84% Open-loop control provides a reliable solution 00:49:39.050 --> 00:49:41.390 align:middle line:90% and is less noise sensitive. 00:49:41.390 --> 00:49:45.380 align:middle line:84% The LLC topology is able to use the transformer with large 00:49:45.380 --> 00:49:48.560 align:middle line:84% leakage inductance and minimize the transformer's 00:49:48.560 --> 00:49:53.090 align:middle line:84% primary-to-secondary-side parasitic capacitances. 00:49:53.090 --> 00:49:56.000 align:middle line:90% It minimizes the noise coupling. 00:49:56.000 --> 00:49:58.970 align:middle line:84% The open-loop LLC converter provides 00:49:58.970 --> 00:50:04.310 align:middle line:84% a simple, robust solution with less EMI, high CMTI, 00:50:04.310 --> 00:50:10.080 align:middle line:84% good voltage regulation, and multiple output capability. 00:50:10.080 --> 00:50:13.720 align:middle line:84% I want to thank you for your time and attention. 00:50:13.720 --> 00:50:23.000 align:middle line:90%