WEBVTT

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[MUSIC PLAYING]

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We all know that the
internet of things, as well

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as the technologies that
have enabled intelligence

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at the edge, present
unlimited opportunities

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to transform business
with analytics and AI.

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But these all require AI at the
edge, along with cost and power

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constraints.

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The need for intelligent,
low-latency, edge computing

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creates an opportunity
for innovative, chip-level

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architectures that
address costs,

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as well as the benefits of
compute efficiency, which

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means getting more
computation at lower power.

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Intel addresses these
challenges with its newest,

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compute-efficient architecture,
the Intel Movidius Myriad X VPU

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for vision and AI at the edge.

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Our VPU offers
optimized dataflow

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between compute-efficient
engines,

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including a specialized,
deep learning accelerator,

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making it one of the most
innovative architectures

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in computer vision today.

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First, the chip architecture
is tailored for dataflow.

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In traditional
chip architectures,

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optimized computation
of data is achieved

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by moving the data to
specialized compute units.

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But moving data back and forth
from extraneous data buffers

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comes at a cost, namely,
power consumption.

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With the Intel
Movidius VPU, we've

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achieved lower power by
minimizing data movement

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on the chip.

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We do this by utilizing
a singular, centralized

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scratchpad memory.

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This multi-ported,
intelligent memory fabric

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speeds dataflow through the chip
to reduce power consumption.

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What's more,
Movidius VPU's tools

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provide automated
dataflow management,

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which helps make
programming more efficient

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by handling the
dataflow and data

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dependencies of the
functions in an application.

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Next, we add superior compute
efficiency and flexibility.

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How do we offer sufficient
vision application performance

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at a reasonable power and cost?

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The Movidius VPU
architecture combines a set

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of hardware-optimized vision and
image processing accelerators,

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together with an array of 16
programmable VLIW processors,

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with an instruction set
tuned for computer vision.

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So developers can
take advantage,

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when porting their algorithms,
to have both performance

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optimization and
software flexibility

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at their fingertips.

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Finally, the
Movidius VPU employs

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a specialized, deep learning,
inference accelerator,

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called the Neural
Compute Engine,

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with enough raw performance to
support multiple AI inference

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applications simultaneously,
such as detection

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and classification.

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And the Neural Compute
Engine runs AI algorithms

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in parallel with
the other imaging

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and computer vision
algorithms on the chip.

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For edge servers and
intelligent appliances,

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multiple Intel
Movidius VPU chips

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are brought together in PCIe
form factor accelerator cards

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to help developers achieve
sufficient performance

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with compute efficiency.

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And with our Intel
distribution of OPENVINO

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toolkit to compile
their AI deep learning

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algorithms to run on
these accelerator cards,

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developers can scale AI
performance at the edge.

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[MUSIC PLAYING]

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