This video will focus on what the I2C designer tool is,
and how it can help users design an I2C bus.
For users who are new to designing an I2C bus,
this tool provides many system checks,
which can help avoid potential problems and save time.
For more experienced users in I2C,
this tool can still be helpful in providing
assistance in PCB bus capacity and estimation
and quick pull-up resistor calculation.
The I2C designer tool is an online tool
created to help the user resolve potential I2C challenges,
such as address conflicts, VCC conflicts, bus capacitance
limits, part selection, pull-up resistor calculations, speed
conflicts, buffer placement with respect to VCC,
and buffer placement with regard to the static voltage offset.
The first design challenge is to ensure the I2C bus does not
experience address conflicts, as the I2C standard states
slave addresses must be unique in order
to prevent data corruption during retransactions.
The I2C designer tool will look for any address conflicts
and present workarounds in the case of address conflicts
with the use of an I2C switch or mox.
VCC conflicts can result in damage to devices which cannot
withstand the higher biasing voltage.
The I2C designer tool will suggest solutions
to resolve this using either an I2C level
shifter or an I2C switch with the level translation
capability.
Bus capacitance is a common issue
with largely loaded I2C buses, where the I2C spec
states the bus capacitance must be
less than 400 pico farads or less for standard mode
and fast mode.
The I2C designer tool has a built in capacitance
estimated feature, which is based on PCP parasitics.
When the capacitance value surpasses the 400 pico farad
limit, the tool will suggests I2C buffers, the segment,
the capacitance, to comply with I2C standard.
One of the most commonly asked questions on the E2E forums
is, what pull-up resistor to use for a given I2C bus?
The I2C designer tool provides the maximum
and minimum pull-up resistor values
for each segment for the I2C bus based
on the estimated bus capacitance and the maximum I2C frequency.
To avoid signal integrity concerns,
I2C slaves, which operate at different speeds,
should not co-exist on the same I2C bus.
The I2C designer tool will take this
into consideration and separate slaves
of different maximum operating speeds using
an I2C switch or an I2C repeater with a disable feature.
When an I2C potential conflict is present,
the I2C designer tool will provide potential solutions
the user can select from to resolve the issue.
Some I2C buffers have strict rules
on how they can be interfaced with other buffers.
The I2C designer tool will ensure any static voltage
offset buffers are not connected to each other
on their static voltage offset sides.
The I2C designer tool currently does have some limitations.
It does not support multiple masters.
The slave devices do not include devices outside
of the interface portfolio, such as temperature sensors, motor
drives, accelerometers, et cetera.
The tool does not support checks for any off board communication.
Lastly, the tool does not take power supply
sequencing into consideration.
The I2C designer tool allows for bus designs
to be quickly generated and common problems
to be automatically addressed.
Built-in bus capacitance estimates and pull-up resistor
value checkers makes this a useful tool
for both experienced I2C designers
and those new to the protocol.
So try our free I2C designer tool on ti.com
to help simplify your I2C tree.