WEBVTT

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This video will focus on what
the I2C designer tool is,

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and how it can help
users design an I2C bus.

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For users who are new
to designing an I2C bus,

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this tool provides
many system checks,

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which can help avoid potential
problems and save time.

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For more experienced
users in I2C,

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this tool can still be
helpful in providing

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assistance in PCB bus
capacity and estimation

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and quick pull-up
resistor calculation.

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The I2C designer tool
is an online tool

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created to help the user resolve
potential I2C challenges,

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such as address conflicts,
VCC conflicts, bus capacitance

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limits, part selection, pull-up
resistor calculations, speed

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conflicts, buffer placement
with respect to VCC,

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and buffer placement with regard
to the static voltage offset.

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The first design challenge is
to ensure the I2C bus does not

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experience address conflicts,
as the I2C standard states

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slave addresses must
be unique in order

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to prevent data corruption
during retransactions.

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The I2C designer tool will
look for any address conflicts

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and present workarounds in
the case of address conflicts

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with the use of an
I2C switch or mox.

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VCC conflicts can result in
damage to devices which cannot

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withstand the higher
biasing voltage.

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The I2C designer tool
will suggest solutions

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to resolve this using
either an I2C level

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shifter or an I2C switch
with the level translation

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capability.

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Bus capacitance
is a common issue

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with largely loaded I2C
buses, where the I2C spec

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states the bus
capacitance must be

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less than 400 pico farads
or less for standard mode

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and fast mode.

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The I2C designer tool has
a built in capacitance

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estimated feature, which
is based on PCP parasitics.

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When the capacitance value
surpasses the 400 pico farad

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limit, the tool will suggests
I2C buffers, the segment,

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the capacitance, to
comply with I2C standard.

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One of the most commonly asked
questions on the E2E forums

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is, what pull-up resistor
to use for a given I2C bus?

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The I2C designer tool
provides the maximum

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and minimum pull-up
resistor values

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for each segment for
the I2C bus based

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on the estimated bus capacitance
and the maximum I2C frequency.

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To avoid signal
integrity concerns,

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I2C slaves, which operate
at different speeds,

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should not co-exist
on the same I2C bus.

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The I2C designer
tool will take this

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into consideration
and separate slaves

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of different maximum
operating speeds using

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an I2C switch or an I2C
repeater with a disable feature.

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When an I2C potential
conflict is present,

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the I2C designer tool will
provide potential solutions

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the user can select from
to resolve the issue.

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Some I2C buffers
have strict rules

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on how they can be interfaced
with other buffers.

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The I2C designer tool will
ensure any static voltage

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offset buffers are not
connected to each other

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on their static
voltage offset sides.

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The I2C designer tool currently
does have some limitations.

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It does not support
multiple masters.

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The slave devices do not
include devices outside

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of the interface portfolio, such
as temperature sensors, motor

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drives, accelerometers,
et cetera.

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The tool does not support
checks for any off board

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communication.

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Lastly, the tool does
not take power supply

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sequencing into consideration.

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The I2C designer tool
allows for bus designs

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to be quickly generated
and common problems

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to be automatically addressed.

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Built-in bus capacitance
estimates and pull-up resistor

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value checkers makes
this a useful tool

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for both experienced
I2C designers

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and those new to the protocol.

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So try our free I2C
designer tool on ti.com

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to help simplify your I2C tree.